Various types of prior floating gate memories are known, such as erasable programmable read-only memory ("EPROM"), electrically-erasable programmable read-only memory ("EEPROM"), and the flash electrically-erasable programmable read-only memory ("flash EEPROM"). One prior flash memory technology is the ETOX.TM. II technology of Intel Corporation of Santa Clara, Calif. FIG. 1A shows a prior ETOX.TM. II flash memory cell 10 of Intel Corporation. Prior flash memory cell 10 has a top gate 12, a floating gate 14, a source 16, and a drain 18. Source 16 and drain 18 reside within a substrate 20. Substrate 20 is grounded. Flash memory cell 10 is comprised of a single transistor. FIG. 1B shows a symbolic representation of flash memory cell 10 that is used to represent flash memory cell 10 in circuit schematics.
Referring again to FIG. 1A, floating gate 14 is used for charge storage. The logic state of flash memory cell 10 is determined by the amount of charge stored on floating gate 14. Electrons are placed on floating gate 14 during a programming process by a mechanism known as hot electron injection. Electrons are removed from floating gate 14 during an erase process by a mechanism known as tunneling. Source 16 comprises a top n+ region and a bottom n region that together create a graded junction capable of withstanding a high source voltage during erase. FIG. 1C illustrates certain current and voltage characteristics of flash memory cell 10. Curve 32 is an I-V characteristic of flash memory cell 10 when floating gate 14 stores little or no charge, i.e. the cell is in an erased state. In this state, flash memory cell 10 is said to store a logic 1. Curve 34 is an I-V characteristic of flash memory cell 10 when floating gate 14 stores substantial charge. In this state, flash memory 10 is said to store a logic 0. Curves 32 and 34 show that charge stored on floating gate 14 shifts the I-V characteristic of memory cell 10 to the right. In other words, charge stored on floating gate 14 increases the threshold voltage of the flash memory cell 10.
The logic state of a memory cell is sensed (or detected) during either a read or verify operation. A read operation reads the data stored in the cell for delivery to another unit. A verify operation reads the data stored in the cell after programming to verify that the cell has been programmed to the proper state. Sensing is the process of determining the logic state of, or data stored in, a memory cell. Reference curve 36 is a I-V characteristic of a flash reference cell that may be used for sensing the state of flash memory cell 10. A logic 1 is sensed if the drain current of flash memory cell 10 is greater than the drain current of the flash reference cell (corresponding the I-V characteristic of flash memory cell 10 being to the left of reference curve 36). A logic 0 is sensed if the current of flash memory cell 10 is smaller than the current of the flash reference cell (corresponding to the I-V characteristic of flash memory cell 10 being to the right of reference curve 36). Typical prior commercial flash memory devices have stored only two logic states, logic 0 and logic 1 (i.e., one bit per cell), in each flash memory cell due in part to difficulties with accurately programming and sensing intermediate amounts of charge on floating gate 14.
FIG. 1A shows one prior configuration for sensing the logic state of flash memory cell 10. For sensing, the drain voltage, V.sub.D, is set to about 1.0 volts, the source 16 is grounded, and the top gate voltage, V.sub.TG, is set to a fixed voltage on the order of 5.0 volts. (Typically the supply voltage, V.sub.CC, is used as the fixed voltage.) The drain current is sensed to determine whether flash memory cell 10 stores a logic 0 or a logic 1. A high drain current (indicating little or no charge on floating gate 14) indicates a logic 1 while a low drain current (indicating substantial charge on floating gate 14) indicates a logic 0.
FIG. 2A shows a prior sensing circuit 40 for sensing the logic state of a flash memory cell 48. Flash memory cell 48 is one cell of an array of flash memory cells. Sensing circuit 40 includes a first chain of serially-connected n-type transistors comprising: a load transistor 42, a cascode transistor 44, and a column select transistor 46. At the end of the first transistor chain is flash memory cell 48 which has been selected for sensing by the appropriate column and row select lines of the flash memory array. A drain bias circuit 47, including cascode transistor 44 and a feedback inverter 45, isolates load transistor 42 from selected flash memory cell 48 and establishes a constant drain bias voltage of about 1.0 volts at the drain of flash memory cell 48. A fixed voltage V.sub.CC of about 5.0 volts is applied to the top gate of flash memory cell 48 causing a current I1 to flow in flash memory cell 48 and through the first transistor chain. The magnitude of current I1 is a function of the logic state of flash memory cell 48, (i.e., a function of the amount of charge stored on the floating gate of flash memory cell 48). The current I1 establishes a voltage at node SEN1 50 according to the I-V characteristic of load transistor 42 shown in FIG. 2B.
Referring again to FIG. 2A, voltage V.sub.SEN1 at node SEN1 50 is compared to a reference voltage V.sub.REF established by a second transistor chain at node REF 60. The second chain of serially-connected n-type transistors includes a load transistor 52, a cascode transistor 54, and a reference select transistor 56, which respectively match the corresponding transistors of the first chain. Flash reference cell 58 is coupled to the end of the second transistor chain and is typically charged to have a reference characteristic similar to reference curve 36 of FIG. 1C. A drain bias circuit 57, including cascode transistor 54 and a feedback inverter 55, isolates load transistor 52 from flash reference cell 58 and establishes a constant drain bias voltage of about 1.0 volts at the drain of flash reference cell 58. The current in flash reference cell 58 is convened to the reference voltage V.sub.REF at node REF 60. Differential amplifier 62 compares V.sub.SEN1 to V.sub.ref to determine the state of flash memory cell 48. Detecting V.sub.SEN1 greater than V.sub.REF indicates logic state 0. Detecting V.sub.SEN1 less than V.sub.REF indicates logic state 1.
Prior sensing circuit 40 is suitable for fast sensing of widely separated states, but suffers from significant problems when sensing of closely-spaced states is required. The voltage range of V.sub.sen1 is typically designed to be between about 1.5 and 3.0 volts. The low end voltage on node SEN1 50 is limited by the practical concerns of keeping differential amplifier 62 in its operational range and maintaining a constant drain bias voltage on flash memory cell 48. The high end voltage on node SEN1 50 is limited by V.sub.CC, the V.sub.t drop of load transistor 42, and the common mode rejection of the differential amplifier. FIG. 2B illustrates the voltage V.sub.SEN1 at node SEN1 50 as a function of current I1. A typical two state (i.e., one bit) memory cell defines logic states to correspond to the I1 and V.sub.SEN1 corresponding to numbers 1 and 4 of the graph. For two states, the difference between the V.sub.SEN1 voltages corresponding to numbers 1 and 4 is relatively large. A four state (i.e., two bit) memory cell could define four logic states (such as 11, 10, 01, and 00) to correspond to numbers 1-4. With four states, the voltage differences between adjacent V.sub.SEN1 voltages is much smaller, making logic state sensing more difficult.
In an array of memory cells, other problems increase the difficulty of sensing states with prior sensing circuit 40 when multiple bits are stored in the memory cells. Typical commercial flash memory devices comprise millions of flash memory cells in a memory array. Due to non-ideal processing conditions during manufacturing, individual memory cells across the array have different characteristics. Varying cell characteristics, fluctuations in power supply voltages, variations in array sensitivity to temperature, and variations in array transconductance, can each cause the V.sub.SEN1 voltage to vary from ideal. To allow for such variations, a range of values is assigned to each state. In other words, each state has a state width to account for variations that affect sensing. The state width, in part, determines how many states a memory cell can store.
One factor contributing to the state width is fluctuation in power supply voltages. Power supply voltages vary within a specified tolerance over time. For example, a 5.0.+-.5% supply voltage may fluctuate between 4.75 and 5.25 volts over time. If the supply voltage during programming is different than during sensing of a memory cell, the sensed state will be offset from its ideal value.
Another factor contributing to the state width is cell to cell variations in temperature sensitivity in a memory array. As temperature increases electron mobility, .mu..sub.e, decreases and threshold voltage, V.sub.tFG, decreases. The impact of temperature changes on individual flash memory cells can be understood by examining Equation 1. ##EQU1## For a state very close to the power supply voltage (i.e., the floating gate is charged to approximately the power supply voltage), (V.sub.FG -V.sub.tFG) is very small causing changes in V.sub.tFG to dominate the temperature effect. Therefore, in this case rising temperature causes V.sub.tFG to decrease and I.sub.D to increase. For a state far away from the power supply voltage, temperature effects are dominated by .mu..sub.e since (V.sub.FG -V.sub.tFG) is large. Therefore, in this case rising temperature causes I.sub.D to decrease. In other words, rising temperature decreases drain current in cells having a high drain current during sensing but increases drain current in cells having a small drain current during sensing. Thus, in the prior sensing scheme, temperature affects arrays cells differently depending on their programmed state. Also, even for cells programmed to the same state there are cell-to-cell variations in sensitivity to temperature changes. So variations in temperature affects also contributes to the state width.
Another factor contributing to the state width is variations in cell transconductance across a memory array. Transconductance of a field effect device such as a flash memory cell is defined in equation 2. ##EQU2## Due to non-ideal processing conditions during manufacturing, the width and length (Zeff and Leff) of individual cells (of the millions in a typical memory array) vary. The resulting transconductance variations cause individual cells in the array to have different I-V characteristics.
In summary, power supply variations, temperature effects, temperature effect variations, and transconductance variations each contribute to the state width. Because these factors require a relatively large state width and the prior sensing circuit 40 has a relatively narrow sensing range of 1.5 to 3.0 volts on the sensing node SEN1 50, it is difficult to use prior circuit 40 for sensing of multi-bit memory cells.